The present invention relates to a processor, and more particularly, to a processor for reading instruction codes that are stored in a memory to perform calculations in accordance with the instruction codes.
There are recent processors that perform calculations based on instruction codes having a bit length that is not an integer multiple of one byte. Such a processor functions as described below.
When, for example, storing an instruction code having 18 bits in a memory section configured by a plurality of 16 bit-length sectors, the processor stores 16 bits of the instruction code in a sector located at a first address. The 16 bits are stored during a first write cycle. The processor then stores the remaining 2 bits in a sector located at a second address during a second write cycle. The cycles are in accordance with clock signals.
To store another 18-bit instruction code, the processor stores 16 bits of the instruction code in a sector located at a third address during a third write cycle. The processor then stores the remaining 2 bits in a sector located at a fourth address during a fourth write cycle.
When reading the. stored instruction codes, the processor reads 16 bits of an instruction code from the sector located at the first address during a first read cycle, and reads the remaining two bits from the sector located at the second address during a second read cycle. The processor synthesizes the 16-bit and 2-bit instruction codes to generate an 18-bit instruction code and perform a calculation in accordance with the instruction code.
In such processor, each of the sectors storing 2 bits of instruction code has a vacant area of 14 bits. Therefore, the storage of a plurality of instruction codes in a plurality of sectors increases the number of vacant areas and decreases the data storage efficiency. This increases the required memory capacity.
Further, two clock signal transmission cycles are necessary to write or read an 18-bit instruction code. This limits the calculating speed.
It is an object of the present invention to provide a processor and a information processing method that efficiently stores instruction codes in a memory and decreases the time for transmitting instruction codes.
To achieve the above object, the present invention provides a processor for performing calculations based on a plurality of instruction codes. Each of the instruction codes includes a higher order bit and lower order bits. The number of lower order bits is an integer multiple of one byte. The processor includes a memory for storing the instruction codes. The memory includes a lower order bit storage section, for storing the lower order bits of each of the instruction codes, and a higher order bit storage section, for storing the higher order bit of each of the instruction codes. An instruction code generation circuit is connected to the memory. The instruction code generation circuit receives a first address signal including data corresponding to an address of the memory, reads the lower order bits and the higher order bit of the instruction code located at the address corresponding to the first address signal, and generates the instruction code. An arithmetic unit is connected to the instruction code generation circuit to provide the first address signal to the instruction code generation circuit, to receive the instruction code generated by the instruction code generation circuit, and to perform a predetermined calculation.
The present invention also provides a processor for performing calculations based on a plurality of instruction codes. Each of the instruction codes includes a higher order bit and lower order bits. The number of lower order bits is an integer multiple of one byte. The processor includes a memory for storing the instruction codes. The memory includes a lower order bit storage section, for storing the lower order bits of each of the instruction codes, and a higher order bit storage section, for storing the higher order bits of more than one of the instruction codes at the same address.
The present invention further provides a information processing method for performing calculations based on a plurality of instruction codes. Each of the instruction codes includes a higher order bit and lower order bits. The number of lower order bits is an integer multiple of one byte. The method includes storing the lower order bits of each of the instruction codes in a lower order bit storage section of a memory at a plurality of addresses, storing the higher order bit of more than one of the instruction codes in a higher order bit storage section of the memory at a single address, generating an instruction code in response to an address signal indicating an address of the memory by reading the lower order bits of a predetermined one of the instruction codes and the corresponding higher order bit in the same cycle, and performing a calculation in accordance with the instruction code.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.